Efficient Reduction of HOL Blocking in Multistage Networks
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 9 - Volume 10
Towards an efficient switch architecture for high-radix switches
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Performance evaluation of multi-fiber optical packet switches
Computer Networks: The International Journal of Computer and Telecommunications Networking
A Fokker-Planck equation method predicting Buffer occupancy in a single queue
Computer Networks: The International Journal of Computer and Telecommunications Networking
Captured-frame matching schemes for scalable input-queued packet switches
Computer Communications
Computer Networks: The International Journal of Computer and Telecommunications Networking
Trends in highly scalable crossbar-based packet switch architecture
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Evolutionary approach for buffer management in asynchronous transfer mode networks
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Integration, the VLSI Journal
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Research: Space division approach to implement a shared buffer in an ATM switch
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Cell scheduling for ATM switch with delay-sensitive and loss-sensitive traffic
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A new shared-buffer packet switch in ATM networks
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Scheduling multicast traffic in input-buffered ATM switch
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Design issues for multicast ATM switches
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Review: Review of recent shared memory based ATM switches
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An analytical model for all-optical packet switching networks with finite FDL buffers
Photonic Network Communications
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The authors study the performance of four different approaches for providing the queuing necessary to smooth fluctuations in packet arrivals to a high-performance packet switch. They are (1) input queuing, where a separate buffer is provided at each input to the switch; (2) input smoothing, where a frame of b packets is stored at each of the input line to the switch and simultaneously launched into a switch fabric of size Nb×Nb; (3) output queuing, where packets are queued in a separate first-in first-out (FIFO) buffer located at each output of the switch; and (4) completely shared buffering, where all queuing is done at the outputs and all buffers are completely shared among all the output lines. Input queues saturate at an offered load that depends on the service policy and the number of inputs N, but is approximately 0.586 with FIFO buffers when N is large. Output queuing and completely shared buffering both achieve the optimal throughput-delay performance for any packet switch. However, compared to output queuing, completely shared buffering requires less buffer memory at the expense of an increase in switch fabric size