Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing using deficit round robin
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Hierarchical packet fair queueing algorithms
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing algorithms for packet-switched networks
IEEE/ACM Transactions on Networking (TON)
IEEE/ACM Transactions on Networking (TON)
Leap Forward Virtual Clock: A New Fair Queuing Scheme with Guaranteed Delay and Throughput Fairness
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Fair scheduling with tunable latency: a round-robin approach
IEEE/ACM Transactions on Networking (TON)
Approximate fairness through differential dropping
ACM SIGCOMM Computer Communication Review
High performance service-time-stamp computation for WFQ IP packet scheduling
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup
AICT-ICIW '06 Proceedings of the Advanced Int'l Conference on Telecommunications and Int'l Conference on Internet and Web Applications and Services
The Stratified Round Robin scheduler: design, analysis and implementation
IEEE/ACM Transactions on Networking (TON)
A scalable packet sorting circuit for high-speed WFQ packet scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scheduling in IEEE 802.16e Mobile WiMAX networks: key issues and a survey
IEEE Journal on Selected Areas in Communications - Special issue on broadband access networks: Architectures and protocols
Multiobjective monitoring for SLA compliance
IEEE/ACM Transactions on Networking (TON)
WF2Q: worst-case fair weighted fair queueing
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Hardware-efficient fair queueing architectures for high-speed networks
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 2
IEEE Communications Magazine
Implementing scheduling algorithms in high-speed networks
IEEE Journal on Selected Areas in Communications
Queueing in high-performance packet switching
IEEE Journal on Selected Areas in Communications
IEEE Network: The Magazine of Global Internetworking
Computer Networks: The International Journal of Computer and Telecommunications Networking
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A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing Reduced Latency DRAM (RLDRAM) II and Quad Data Rate (QDR) II SRAM memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.