High performance service-time-stamp computation for WFQ IP packet scheduling

Authors:
C. McKillen;S. Sezer;Xin Yang
Affiliations:
Institute of Electronics, Communications and Information Technology;Institute of Electronics, Communications and Information Technology;Institute of Electronics, Communications and Information Technology
Venue:
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Year:
2006

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Abstract

In this paper the design and implementation of a unique service-time-stamp computation circuit, called the finishing tag, for WFQ based packet scheduling is presented. The implementation is based on UMC 130nm standard cell technology, and placed and routed using Cadence SoC encounter. The design targets the development of programmable IP packet scheduling circuits for next generation network processing platforms for line-rates beyond 200Gbps.