A scalable packet sorting circuit for high-speed WFQ packet scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fully hardware based WFQ architecture for high-speed QoS packet scheduling
Integration, the VLSI Journal
Hi-index | 0.00 |
The massive growth in the use of Internet and the development of new real-time applications has put considerable strain on the techniques currently used for the lookup and retrieval of information essential for classification, routing, Quality of Service (QoS) and Internet security. This paper investigates the design and implementation of a number of closest value lookup circuits, suitable for deployment in a range of networking applications. Detailed descriptions of a number of matching circuit architectures are given and the results of hardware implementations for the Altera Stratix II FPGA are discussed and evaluated.