A scalable packet sorting circuit for high-speed WFQ packet scheduling

Authors:
K. McLaughlin;S. Sezer;H. Blume;X. Yang;F. Kupzog;T. Noll
Affiliations:
The Institute of Electronics, Communications and Information Technology, Queen's University Belfast, Belfast, Northern Ireland, U.K.;The Institute of Electronics, Communications and Information Technology, Queen's University Belfast, Belfast, Northern Ireland, U.K.;The Institute of Electrical Engineering and Computer Systems, RWTH Aachen University, Aachen, Germany;The Institute of Electronics, Communications and Information Technology, Queen's University Belfast, Belfast, Northern Ireland, U.K.;The Institute of Electrical Engineering and Computer Systems, RWTH Aachen University, Aachen, Germany;The Institute of Electrical Engineering and Computer Systems, RWTH Aachen University, Aachen, Germany
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.