A 32GBit/s communication SoC for a waferscale neuromorphic system

Authors:
Stefan Scholze;Holger Eisenreich;Sebastian Höppner;Georg Ellguth;Stephan Henker;Mario Ander;Stefan Hänzsche;Johannes Partzsch;Christian Mayr;René Schüffny
Affiliations:
Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...;Endowed Chair of Highly-Parallel VLSI-Systems and Neural Microelectronics, Institute of Circuits and Systems, Faculty of Electrical Engineering and Information Technology, University of Technology ...
Venue:
Integration, the VLSI Journal
Year:
2012

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Abstract

State-of-the-art large-scale neuromorphic systems require a sophisticated, high-bandwidth communication infrastructure for the exchange of spike events between units of the neural network. These communication infrastructures are usually built around custom-designed FPGA systems. However, the overall bandwidth requirements and the integration density of very large neuromorphic systems necessitate a significantly more targeted approach, i.e. the development of dedicated integrated circuits. We present a VLSI realization of a neuromorphic communication system-on-chip (SoC) with a cumulative throughput of 32GBit/s in 0.18@mm CMOS, employing state-of-the-art circuit blocks. Several of these circuits exhibit improved performance compared to current literature, e.g. a priority queue with a speed of 31Mkeys/s at 1.3mW, or a 1GHz PLL at 5mW. The SoC contains additional neuromorphic functionality, such as configurable event delays and event ordering. The complete configuration of the neuromorphic system is also handled by the spike communication channels, in contrast to the separate channels required in the majority of current systems. At 865Mevent/s, the SoC delivers at least a factor of eight more bandwidth than other current neuromorphic communication infrastructures.