Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures
DDECS '08 Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
The Designer's Guide to Jitter in Ring Oscillators
The Designer's Guide to Jitter in Ring Oscillators
A novel ADPLL design using successive approximation frequency control
Microelectronics Journal
Jitter analysis and a benchmarking figure-of-merit for phase-locked loops
IEEE Transactions on Circuits and Systems II: Express Briefs
A leakage-compensated PLL in 65-nm CMOS technology
IEEE Transactions on Circuits and Systems II: Express Briefs
A phase-locked loop with background leakage current compensation
IEEE Transactions on Circuits and Systems II: Express Briefs
CMOS PLL Synthesizers: Analysis and Design
CMOS PLL Synthesizers: Analysis and Design
Low-power, high-speed transceivers for network-on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance, energy efficiency, and scalability with GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 32GBit/s communication SoC for a waferscale neuromorphic system
Integration, the VLSI Journal
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This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm2 it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.