A leakage-compensated PLL in 65-nm CMOS technology

Authors:
Chao-Ching Hung;Shen-Iuan Liu
Affiliations:
Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

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A phase-locked loop with background leakage current compensation

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A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology

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Abstract

A leakage compensation technique is presented to compensate the on-chip loop filter leakage for phase-locked loops in 65-nm complementary metal-oxide-semiconductor technology. Using the leakage compensation technique, the measured root-mean-square jitter is reduced to 3.10 ps when the output frequency is 950 MHz. This chip consumes 10 mW, and the active area is 0.14mm2.