Analog-to-digital converter survey and analysis
IEEE Journal on Selected Areas in Communications
Modeling and filtering double-frequency jitter in one-way master-slave chain networks
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
A 120–420 MHz delay-locked loop with multi-band voltage-controlled delay unit
International Journal of Circuit Theory and Applications
A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL. The phase noise that is generated by the thermal noise in the oscillator and loop components is calculated. The power dissipation is estimated, focusing on the required dynamic power. The absolute PLL output jitter is calculated, and the optimum PLL bandwidth that gives minimum jitter is derived. It is shown that, with a steep enough input reference clock, this minimum jitter is independent of the reference frequency and output frequency for a given PLL power budget. Based on these insights, a benchmark FOM for PLL designs is proposed.