A novel method for stochastic nonlinearity analysis of a CMOS pipeline ADC
Proceedings of the 38th annual Design Automation Conference
Scalable hybrid computation with spikes
Neural Computation
Low-Power Asynchronous A/D Conversion
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
A New Class of Asynchronous A/D Converters Based on Time Quantization
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Comprehensive error analysis of ultra-wideband direct conversion receivers
Signal Processing - Special section: Hans Wilhelm Schüßler celebrates his 75th birthday
A 2.7V 350µW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach
Proceedings of the 2004 international symposium on Low power electronics and design
A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18µm Digital CMOS
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes
IEEE Transactions on Computers
A 120nm low power asynchronous ADC
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Systematic power reduction and performance analysis of mismatch limited ADC designs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Effects of A-D conversion nonidealities on distributed sampling in dense sensor networks
Proceedings of the 5th international conference on Information processing in sensor networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of an ADC for subsampling video applications
Analog Integrated Circuits and Signal Processing
High-resolution background calibrated ADCs for software-defined radios
Microelectronics Journal
The effects of aperture jitter and clock jitter in wideband ADCs
Computer Standards & Interfaces
Novel radio architectures for UWB, 60 GHz, and cognitive wireless systems
EURASIP Journal on Wireless Communications and Networking
Towards low-power on-chip auditory processing
EURASIP Journal on Applied Signal Processing
DS-CDMA receiver based on a five-port technology
EURASIP Journal on Applied Signal Processing
Analysis and design of timing recovery schemes for DMT systems over indoor power-line channels
EURASIP Journal on Applied Signal Processing
A multiple-antenna system for ISM-band transmission
EURASIP Journal on Applied Signal Processing
The impact of software radio on wireless networking
ACM SIGMOBILE Mobile Computing and Communications Review
1GS/s pipelined delta sigma modulator ADC using residue averaging technique
Analog Integrated Circuits and Signal Processing
A 1.8-V 3.1 mW successive approximation ADC in system-on-chip
Analog Integrated Circuits and Signal Processing
Jitter analysis and a benchmarking figure-of-merit for phase-locked loops
IEEE Transactions on Circuits and Systems II: Express Briefs
On-chip measurement of jitter transfer and supply sensitivity of PLL/DLLs
IEEE Transactions on Circuits and Systems II: Express Briefs
On the accuracy and resolution of powersum-based sampling methods
IEEE Transactions on Signal Processing
A second-order antialiasing prefilter for a software-defined radio receiver
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Wideband, bandpass, and versatile hybrid filter bank A/D conversion for software radio
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2008 custom integrated circuits conference (CICC 2008)
Delta-sigma A/D conversion via time-mode signal processing
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Power dissipation bounds for high-speed Nyquist analog-to-digital converters
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Flexible RF band pass analog to digital converter for multi-channel receivers
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Parameters estimation from 1-bit dithered quantized data with dependent noise
SIP '07 Proceedings of the Ninth IASTED International Conference on Signal and Image Processing
Adaptive rate sampling and filtering based on level crossing sampling
EURASIP Journal on Advances in Signal Processing
On block noncoherent communication with low-precision phase quantization at the receiver
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 4
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Circuit noise effect on sampling clock in frequency-domain radio receiver IF digitization
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Design methodology for software radio systems
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
A high speed analog to digital converter for ultra wide band applications
EUC'07 Proceedings of the 2007 conference on Emerging direction in embedded and ubiquitous computing
All optical analog-to-digital conversion: principal and recent progress
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
Photonic analog-to-digital converter based on wavelength sampling and quantizing
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
Phase-shifting optical quantization for high-speed microwave signals
APCC'09 Proceedings of the 15th Asia-Pacific conference on Communications
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Beyond Nyquist: efficient sampling of sparse bandlimited signals
IEEE Transactions on Information Theory
IEEE Communications Magazine
Digital post-processing for reducing A/D converter nonlinear distortion in wideband radio receivers
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Analog beamforming in MIMO communications with phase shift networks and online channel estimation
IEEE Transactions on Signal Processing
IEEE Transactions on Circuits and Systems II: Express Briefs
A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR
Proceedings of the Conference on Design, Automation and Test in Europe
High performance HF-VHF all digital RF receiver tested at 20 GHZ clock frequencies
MILCOM'06 Proceedings of the 2006 IEEE conference on Military communications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A high-speed sample-and-hold circuit based on CMOS transmission lines
Analog Integrated Circuits and Signal Processing
An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities
Analog Integrated Circuits and Signal Processing
4- and 6-GS/s 4-bit frequency-translating hybrid ADCs in 90-nm CMOS
Analog Integrated Circuits and Signal Processing
A charge-pump and comparator based power-efficient pipelined ADC technique
Microelectronics Journal
A high-speed differential resistor ladder
Microelectronics Journal
Analog Integrated Circuits and Signal Processing
Energy Efficient Scalable Sub-band based Ultra-Wideband System
Wireless Personal Communications: An International Journal
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Analog-to-digital converters (ADCs) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADCs, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Gs/s), resolution appears to be limited by thermal noise. At sampling rates ranging from ~2 Ms/s to ~4 giga samples per second (Gs/s), resolution falls off by ~1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADCs operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The trend toward single-chip ADCs brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only ~1.5 bits for any given sampling frequency over the last six-eight years