A 120nm low power asynchronous ADC
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Analog-to-digital converter survey and analysis
IEEE Journal on Selected Areas in Communications
A 1.2 V 8-bit 1 MS/s SAR ADC with Res---Cap segment DAC for temperature sensor in LTE
Analog Integrated Circuits and Signal Processing
An efficient threshold voltage generation for SAR ADCs
Analog Integrated Circuits and Signal Processing
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An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.