A high-speed sample-and-hold circuit based on CMOS transmission lines

  • Authors:

  • Pingshan Wang;Haibo Wang;Yueran Gao;Yongtao Geng;George Thomas;Chaojiang Li

  • Affiliations:

  • Department of Electrical and Computer Engineering, Clemson University, Clemson, USA 29634;Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, USA 62901;Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, USA 62901;Department of Electrical and Computer Engineering, Clemson University, Clemson, USA 29634;Department of Electrical and Computer Engineering, Clemson University, Clemson, USA 29634;Department of Electrical and Computer Engineering, Clemson University, Clemson, USA 29634

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2011

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Abstract

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13聽μm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of ~50聽ps width with ~17聽ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20聽Giga-sample/s with a 25聽dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.