A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

Authors:
Hui-Chin Tseng;Hsin-Hung Ou;Chi-Sheng Lin;Bin-Da Liu
Affiliations:
National Cheng Kung University, Tainan, Taiwan, R.O.C;National Cheng Kung University, Tainan, Taiwan, R.O.C;National Cheng Kung University, Tainan, Taiwan, R.O.C;National Cheng Kung University, Tainan, Taiwan, R.O.C
Venue:
Proceedings of the 2004 international symposium on Low power electronics and design
Year:
2004

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Abstract

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 µm process parameters, the results show that INL