Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter
Analog Integrated Circuits and Signal Processing
Design Method and Automation of Comparator Generation for Flash A/D Converter
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach
Proceedings of the 2004 international symposium on Low power electronics and design
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
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This paper presents a process variation tolerant, SoC ready, 1 GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologies. The physical design is carried out with a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit using Design for Manufacturability (DFM) methodologies. Post-layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC has been simulated for a supply voltage variation of 10%, and threshold voltage mismatch of 5%. The results show maximum variations of 10.5% and 5.7% in the INL and DNL respectively, with nominal INL = 0.344 LSB and nominal DNL = 0.459 LSB, at a supply voltage of 1.2 V. The ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators used in the ADC have been designed using the threshold inverting technique.