4- and 6-GS/s 4-bit frequency-translating hybrid ADCs in 90-nm CMOS

Authors:
Shahrzad Jalali Mazlouman;Samad Sheikhaei;Shahriar Mirabbasi
Affiliations:
Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada V6T 1Z4;Electrical and Computer Engineering Department, University of Tehran, Tehran, Iran 14399-57131;Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada V6T 1Z4
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2011

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Abstract

Two frequency-translating hybrid analog-to-digital converters (FTH-ADCs) are implemented using building blocks that are designed and fabricated in a 90-nm CMOS technology. These blocks include a mixer, a filter, and an ADC that are cascaded to build each analog processing path of the FTH-ADC. The mixer-filter path is designed with sufficient linearity and signal-to-noise-and-distortion ratio (SNDR) to accommodate for the desired resolution of the path ADC. A 4-bit flash ADC structure is used in each path. This path has a signal bandwidth of 0.5 GHz and frequency-translates the input signal into baseband and digitizes it with the sample rate of 2 GHz. Multiple such mixer-filter-ADC paths are then combined together with proper mixing frequencies in order to implement two- and three-channel ADC systems. The two- and three-channel systems have overall input bandwidths of 2 and 3 GHz and effective conversion rates of 4 and 6 GS/s, respectively, while maintaining their single-path resolution across their entire input bandwidths. The implemented architecture provides an extendible solution to improve the speed of ADCs by incorporating them in an FTH-ADC architecture.