4- and 6-GS/s 4-bit frequency-translating hybrid ADCs in 90-nm CMOS
Analog Integrated Circuits and Signal Processing
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This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 驴m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm2 silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.