A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

Authors:
Timmy Sundström;Atila Alvandpour
Affiliations:
Division of Electronic Devices, Department of Electrical Engineering, Linköping University, Linköping, Sweden 584 39;Division of Electronic Devices, Department of Electrical Engineering, Linköping University, Linköping, Sweden 584 39
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2010

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Abstract

A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade-offs. The redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators with clock-gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low-power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.