A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS
Analog Integrated Circuits and Signal Processing
Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver
Analog Integrated Circuits and Signal Processing
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Averaging network is adopted to reduce the front-end amplifier's offset in the flash analog-to-digital converter (ADC) commonly at the cost of the boundary threshold error. Such error worsens the integral-nonlinearity and introduces distortion. An averaging termination scheme using intended asymmetric spatial filter response is proposed to overcome this problem. It matches the impulse response window width, W IR, to the active zero-crossing response window width, W ZX at the boundary of network. Analysis and simulation show that by tuning the ratio between termination resistor R T and averaging resistor R 1, the boundary error is reduced as close as to 1%. This method provides sufficient reliability since the resistance matching can be fabricated as high as 1% in modern CMOS technology. Its feasibility for the flash ADC has been validated by a 1GS/s 4-bit flash converter.