An efficient power reduction technique for CMOS flash analog-to-digital converters
Analog Integrated Circuits and Signal Processing
General analysis on the impact of phase-skew in time-interleaved ADCs
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS
Analog Integrated Circuits and Signal Processing
Design and Optimization of Passive UHF RFID Systems
Design and Optimization of Passive UHF RFID Systems
The theory of bandpass sampling
IEEE Transactions on Signal Processing
Analog Integrated Circuits and Signal Processing
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This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s. The ADC's specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels, a twice sampling front end is used. An improved averaging termination technique using intended asymmetric spatial filter response is proposed. This circuit is designed in a 0.13 μm CMOS technology with 1.2 V power supply. Simulation results show a 26 dB SNDR at 2.112 GHz sampling rate with 36 mW power consumption and the effective figure of merit value is 0.24 pJ/step.