Proceedings of the conference on Design, automation and test in Europe
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Proceedings of the 46th Annual Design Automation Conference
Utilizing process variations for reference generation in a flash ADC
IEEE Transactions on Circuits and Systems II: Express Briefs
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
ZerehCache: armoring cache architectures in high defect density technologies
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Process variation-aware test for resistive bridges
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of device variability in the communication structures for future synchronous SoC designs
SOC'09 Proceedings of the 11th international conference on System-on-chip
A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS
Analog Integrated Circuits and Signal Processing
Product on-chip process compensation for low power and yield enhancement
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
While CMOS technology has served semiconductor industry marvelously (by allowing nearly exponential increase in performance and device integration density), it faces some major roadblocks at sub-90nm process nodes due to the intrinsic physical limitations of the devices. One of the major barriers that the CMOS devices face at nanometer scale is increasing process parameter variations. Due to limitations of the fabrication process (e.g. sub-wavelength lithography and etching) and variations in the number of dopants in the channel of short channel devices, device parameters such as length (L), width 0, oxide thickness (T,), threshold voltage (VTH) etc. suffer large variations. Variations in the device parameters, both systematic and random, translate into variations in circuit parameters like delay and leakage power, leading to loss in parametric yield. To deal with increasing parameter variations, it is important to accurately model the impact of device parameter variations at circuit level and develop process-tolerant design techniques for both logic and memory. This article analyzes the impact of process parameter variations on logic circuits and memory and focuses on some major works in the area of process-tolerant design methodology at circuit/architecture level.