Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Process Variations and Process-Tolerant Design
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Power dissipation bounds for high-speed Nyquist analog-to-digital converters
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Bulk voltage trimming offset calibration for high-speed flash ADCs
IEEE Transactions on Circuits and Systems II: Express Briefs
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This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.