Analog-to-digital converter survey and analysis
IEEE Journal on Selected Areas in Communications
Utilizing process variations for reference generation in a flash ADC
IEEE Transactions on Circuits and Systems II: Express Briefs
The blocker challenge when implementing software defined radio receiver RF frontends
Analog Integrated Circuits and Signal Processing
Power consumption of analog circuits: a tutorial
Analog Integrated Circuits and Signal Processing
Tracking the best level set in a level-crossing analog-to-digital converter
Digital Signal Processing
Proceedings of the Twelfth ACM Workshop on Hot Topics in Networks
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A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.