Bulk voltage trimming offset calibration for high-speed flash ADCs

Authors:
Junjie Yao;Jin Liu;Hoi Lee
Affiliations:
Electrical Engineering Department, University of Texas at Dallas, Richardson, TX;Electrical Engineering Department, University of Texas at Dallas, Richardson, TX;Electrical Engineering Department, University of Texas at Dallas, Richardson, TX
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2010

Citing 1
Cited 1

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A high-speed offset cancelling distributed sample-and-hold architecture for flash A/D converters

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Abstract

A bulk voltage trimming offset calibration technique is presented for flash analog-to-digital converters (ADCs). Offset calibration is achieved by digitally adjusting the bulk voltages of the preamplifier input devices. Without introducing additional capacitive loading in the analog path, this technique improves the accuracy of flash ADCs while not impairing their high-speed performance. A 4-bit ADC in 90-nm CMOS with the proposed technique achieves 3.71 effective number of bits (ENOB) at 5-GS/s sampling rate with 2.5-GHz effective resolution bandwidth (ERBW). The calibration generally improves ENOB by approximately 0.5 bit after calibration. The ADC consumes 86 mW at 5 GS/s with a 2.5-GHz input achieving a 1.32-pJ/convstep figure of merit. The ADC occupies 0.135-mm2 chip area.