1GS/s pipelined delta sigma modulator ADC using residue averaging technique

  • Authors:

  • Saiyu Ren;Ray Siferd

  • Affiliations:

  • Department of Electrical Engineering, Wright State University, Dayton, USA;Department of Electrical Engineering, Wright State University, Dayton, USA

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2008

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Abstract

A two stage pipelined delta sigma modulator (PDSM) ADC is presented for broadband, high-resolution applications, which incorporate a first, order delta sigma modulator in each stage and combines the most significant bits of the first stage with the second stage output. A key feature of the PDSM ADC architecture is a SINC filter residue averaging technique, which results in mitigating the effect of track/hold and analog, subtract circuit errors, DAC non-linearity, and component mismatch. The input bandwidth of 62.5 MHz and the sampling frequency of 1 GHz result in an over sampling ratio of 8 for the first order modulators. MATLAB simulations for the two stage ADC show 13---15 bit resolution. A transistor level design in 0.18 um CMOS for the two stage ADC was captured with Cadence tools and simulations show 12 bit resolution with a 50 MHz input.