A high-speed differential resistor ladder

  • Authors:

  • D. De Caro;M. Coppola;N. Petra

  • Affiliations:

  • Department of Electronic and Telecommunications Engineering, University of Napoli "Federico II", via Claudio 21, I-80125 Napoli, Italy;Department of Electronic and Telecommunications Engineering, University of Napoli "Federico II", via Claudio 21, I-80125 Napoli, Italy;Department of Electronic and Telecommunications Engineering, University of Napoli "Federico II", via Claudio 21, I-80125 Napoli, Italy

  • Venue:
  • Microelectronics Journal
  • Year:
  • 2012

Quantified Score

Hi-index 0.00

Visualization

Abstract

This paper describes the implementation of a novel high speed differential resistor ladder. In this paper it is shown that the novel ladder yields, theoretically, up to a sixteen fold reduction of the propagation delay with respect to the conventional differential ladder. In order to ease the design process, an accurate analytical model for the ladder INL is also derived in the paper. Simulation results, for a BiCMOS 0.25@mm technology, show that the novel ladder results in a fivefold increase of the maximum sampling frequency when employed to design an 8bit Flash converter. A 65% higher speed is also highlighted when the ladder is employed in a Folding and Interpolating 8bit converter.