Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Clock Feedthrough in CMOS Analog Transmission Gate Switches
Analog Integrated Circuits and Signal Processing
Analog-to-digital converter survey and analysis
IEEE Journal on Selected Areas in Communications
A 1.8-V 3.1 mW successive approximation ADC in system-on-chip
Analog Integrated Circuits and Signal Processing
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This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for high-speed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-of-merit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable high-swing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-驴m CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm2.