A 1.8-V 3.1 mW successive approximation ADC in system-on-chip

Authors:
Shan-Li Long;Jian-Hui Wu;Xiao-Juan Xia;Long-Xing Shi
Affiliations:
National ASIC System Engineering Research Center, Southeast University, Nanjing, China 210096;National ASIC System Engineering Research Center, Southeast University, Nanjing, China 210096;National ASIC System Engineering Research Center, Southeast University, Nanjing, China 210096;National ASIC System Engineering Research Center, Southeast University, Nanjing, China 210096
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2008

Citing 3
Cited 6

CMOS Circuit Design, Layout, and Simulation, Second Edition

CMOS Circuit Design, Layout, and Simulation, Second Edition
Design of an ADC for subsampling video applications

Analog Integrated Circuits and Signal Processing
Analog-to-digital converter survey and analysis

IEEE Journal on Selected Areas in Communications

Gain and offset correction methods for analog-to-digital converters

Analog Integrated Circuits and Signal Processing
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications

Microelectronics Journal
An ultra low die area 8-b ADC and its generic calibration logic

Analog Integrated Circuits and Signal Processing
A 1.2 V 8-bit 1 MS/s SAR ADC with Res---Cap segment DAC for temperature sensor in LTE

Analog Integrated Circuits and Signal Processing
An efficient threshold voltage generation for SAR ADCs

Analog Integrated Circuits and Signal Processing
High-speed and low-power scalable Hamming weight comparator based on a non-weighted switched-capacitor array

Analog Integrated Circuits and Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a 10-bit 2.5 Msample/s successive approximation analog-to-digital converter (ADC) for SoC system. Based on conventional successive approximation ADC architecture a new and faster solution is used. The new solution consists of bootstrap switch, capacitors for sample-hold (S/H) circuit and DAC, using an offset cancellation method and there is no need for any active element. Together with an added bit and an offset compensation comparator the speed and accuracy is increased. The ADC exhibits higher 9 effective number of bits (ENOB) for sample rate to 2.5 Ms/s. The ADC consumes 3.1 mW from a 1.8 V supply and occupies about 0.25 mm2. The measured SNR is 56.05 dB.