On the Development of Analogue Sampled-Data Signal Processing
Analog Integrated Circuits and Signal Processing
A Novel Integrated CMOS Switch Circuit for High PrecisionSample-and-Hold Technique
Analog Integrated Circuits and Signal Processing
A 220-MSample/s CMOS Sample-and-Hold Circuit Using Double-Sampling
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from the 1997 NORCHIP conference
Analog Integrated Circuits and Signal Processing
A 200 MHz 4.8 mW 3 V Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal
Analog Integrated Circuits and Signal Processing
A 1.8-V 3.1 mW successive approximation ADC in system-on-chip
Analog Integrated Circuits and Signal Processing
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This paper describes a simple offset error (OEC) and two gain error (GEC) correction methods for an analog---digital converter (ADC), which use a dedicated sample-and-hold (S/H) circuit. These three methods are specifically proposed for switched- capacitor (SC) S/H circuits. In these methods, few unit capacitors of main S/H-capacitor are separated for correction. OEC method and one of GEC method uses bottom-plate sampling to correct the sampled voltage. The second GEC method uses charge sharing method between capacitors.