A 220-MSample/s CMOS Sample-and-Hold Circuit Using Double-Sampling
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from the 1997 NORCHIP conference
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
A 250 MHz 11 bit 22 mW CMOS low-hold-pedestal fully differential sample-and-hold circuit
Analog Integrated Circuits and Signal Processing
Gain and offset correction methods for analog-to-digital converters
Analog Integrated Circuits and Signal Processing
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A new technique for realizing a high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The design consideration of the building blocks is described in detailed. A prototype circuit in a 0.5-驴 m CMOS process is integrated and experimental results are presented. The sample-and-hold circuit operates up to 200 MHz of sampling frequency with less than 驴56.5 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8Vpp. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.6 ns acquisition time at 0.8 V step input, and 0.8 Vpp full-scale differential input range are achieved. The circuit dissipates 4.8 mW with a 卤 1.5 V power supply.