A 220-MSample/s CMOS Sample-and-Hold Circuit Using Double-Sampling

Authors:
Mikko Waltari;Kari Halonen
Affiliations:
Helsinki University of Technology, Electronic Circuit Design Laboratory, FIN-02150 Espoo, Finland. E-mail: Mikko.Waltari@hut.fi;Helsinki University of Technology, Electronic Circuit Design Laboratory, FIN-02150 Espoo, Finland. E-mail: Mikko.Waltari@hut.fi
Venue:
Analog Integrated Circuits and Signal Processing - Special issue on selected papers from the 1997 NORCHIP conference
Year:
1999

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Abstract

A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampling rate while maintaining comparable power consumption. The circuit is designed in a 0.5 μm CMOS technology. The measurements show 10-bit operation up to the Nyquist frequency at the sampling rate of 220 MS/s with 25 mW @ 3 V power dissipation.