Analog-to-digital converter survey and analysis
IEEE Journal on Selected Areas in Communications
An efficient power reduction technique for CMOS flash analog-to-digital converters
Analog Integrated Circuits and Signal Processing
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This paper focuses on several methods to save power consumption in mismatch limited ADC designs, like flash and folding architectures. Migrating existing designs to a next submicron technology helps to reduce the power consumption significantly. It is shown that decreasing bandwidth and sample rate creates a more than linear reduction of the power consumption. Both of these methods will be addressed in this paper. Also the balance between power consumption of the analog and digital circuitry will be examined. An existing 6-bit 1.6GS/s ADC in 0.18μm CMOS is transferred to a 0.12μm technology. The sampling rate is reduced to 260MS/s, the measured ERBW to 124MHz while running at only 32mW. As the bandwidth is downscaled 5x, the power consumption is reduced by 10x, which results in an improved conversion efficiency. As the design topology is unaltered, the implemented design sets a reference for evaluation of any low-power technique