A selectable-bandwidth 3.5 mW, 0.03 mm2 self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

  • Authors:

  • Pierre Woestyn;Pieter Rombouts;Xinpeng Xing;Georges Gielen

  • Affiliations:

  • Department of ELIS, Ghent University (UGent), Gent, Belgium 9000;Department of ELIS, Ghent University (UGent), Gent, Belgium 9000;Department of Elektrotechniek, ESAT-MICAS, Katholieke Universiteit of Leuven, Leuven, Belgium 3001;Department of Elektrotechniek, ESAT-MICAS, Katholieke Universiteit of Leuven, Leuven, Belgium 3001

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2012

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Abstract

In this paper we present a dual-mode third-order continuous time $$\Upsigma\Updelta$$ modulator that combines noise-shaping and pulse-width-modulation (PWM). In our 0.18 μm CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm2 and a power consumption of 3.5 mW.