Signals & systems (2nd ed.)
Clock programmable if circuits for cmos software defined radio receiver and precise quadrature oscillators
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
The software radio architecture
IEEE Communications Magazine
Analog-to-digital converter survey and analysis
IEEE Journal on Selected Areas in Communications
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A new architecture is presented for a sinc2(f) filter intended to sample channels of varying bandwidth when surrounded by blockers and adjacent bands. The sample rate is programmable from 5 to 40 MHz, and aliases are suppressed by 45 dB or more. The noise and linearity performance of the filter is analyzed, and the effects of various imperfections such as transconductor finite output impedance, interchannel gain mismatch, and residual offsets in the channels are studied. Furthermore, it is proved that the filter is robust to the clock jitter. The 0.13-µm CMOS circuit consumes 6 mA from a 1.2-V supply.