A 120–420 MHz delay-locked loop with multi-band voltage-controlled delay unit

  • Authors:

  • Ko-Chi Kuo;Yi-Hsi Hsu

  • Affiliations:

  • Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan;Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan

  • Venue:
  • International Journal of Circuit Theory and Applications
  • Year:
  • 2012

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Abstract

A low-jitter and low-power dissipation delay-locked loop (DLL) is presented. A proposed multi-band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak-to-peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.