A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators

  • Authors:

  • Michele Nocente;Donald Fontanelli;Pierpaolo Palestri;Roberto Nonis;David Esseni;Luca Selmi

  • Affiliations:

  • Department of Electrical, Mechanical and Management Engineering, University of Udine, via delle Scienze 208, 33100 Udine, Italy;Department of Electrical, Mechanical and Management Engineering, University of Udine, via delle Scienze 208, 33100 Udine, Italy;Department of Electrical, Mechanical and Management Engineering, University of Udine, via delle Scienze 208, 33100 Udine, Italy;(Now with Infineon Technologies, Villach, Austria) Department of Electrical, Mechanical and Management Engineering, University of Udine, via delle Scienze 208, 33100 Udine, Italy;Department of Electrical, Mechanical and Management Engineering, University of Udine, via delle Scienze 208, 33100 Udine, Italy;Department of Electrical, Mechanical and Management Engineering, University of Udine, via delle Scienze 208, 33100 Udine, Italy

  • Venue:
  • International Journal of Circuit Theory and Applications
  • Year:
  • 2010

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Abstract

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase-noise of ring oscillators consisting of MOS-current-mode-logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase-noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.