A novel ADPLL design using successive approximation frequency control

Authors:
H. Eisenreich;C. Mayr;S. Henker;M. Wickert;R. Schüffny
Affiliations:
Circuits and Systems Laboratory, University of Technology Dresden, Dresden, Germany;Circuits and Systems Laboratory, University of Technology Dresden, Dresden, Germany;Circuits and Systems Laboratory, University of Technology Dresden, Dresden, Germany;Circuits and Systems Laboratory, University of Technology Dresden, Dresden, Germany;Circuits and Systems Laboratory, University of Technology Dresden, Dresden, Germany
Venue:
Microelectronics Journal
Year:
2009

Citing 3
Cited 2

Wireless CMOS frequency synthesizer design

Wireless CMOS frequency synthesizer design
RF System Design of Transceivers for Wireless Communications

RF System Design of Transceivers for Wireless Communications
An 80MHz PLL with 72.7ps peak-to-peak jitter

Microelectronics Journal

A 32GBit/s communication SoC for a waferscale neuromorphic system

Integration, the VLSI Journal
A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight reference cycles. ASICs in CMOS AMS 0.35@mm and UMC 0.13@mm have been manufactured and tested. Measurements show competitive results to state-of-the-art mixed-signal implementations.