A 32GBit/s communication SoC for a waferscale neuromorphic system
Integration, the VLSI Journal
Hybrid Dual-Mode Frequency Synthesis for Cognitive Multi-radio Front-Ends
Wireless Personal Communications: An International Journal
A 1.78---3.05 GHz fractional-N frequency synthesizer with power reduced multi-modulus divider
Analog Integrated Circuits and Signal Processing
A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This book presents both fundamentals and the state of the art of PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, Sigma Delta fractional-N synthesizer prototype is implemented in 0.35m m CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which tackle speed and integration bottlenecks of PLL synthesizer elegantly. This book is conceived as a PLL synthesizer manual for both academia researchers and industry design engineers.