Wireless Technologies: Circuits, Systems, and Devices
Wireless Technologies: Circuits, Systems, and Devices
CMOS PLL Synthesizers: Analysis and Design
CMOS PLL Synthesizers: Analysis and Design
A survey on spectrum management in cognitive radio networks
IEEE Communications Magazine
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This paper investigates a novel approach to reconfigurable frequency synthesis for flexible radio transceivers in future cognitive multi-radios. The frequency range covered by the proposed multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards operating in the radio band ranging from 800 MHz to 6 GHz. A hybrid phase locked loop (PLL) based frequency synthesizer is proposed here and a novel switching protocol is presented and validated on an experimental evaluation board. The proposed architecture combines fractional and integer PLL modes of operation along with a switched loop filter topology. Compared to standard PLL techniques, the proposed configuration provides great flexibility options and moreover, it offers relatively low circuit complexity and low power consumption. The proposed architecture provides reconfigurability of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards.