Calendar queues: a fast 0(1) priority queue implementation for the simulation event set problem
Communications of the ACM
Analysis and simulation of a fair queueing algorithm
SIGCOMM '89 Symposium proceedings on Communications architectures & protocols
Virtual clock: a new traffic control algorithm for packet switching networks
SIGCOMM '90 Proceedings of the ACM symposium on Communications architectures & protocols
IEEE/ACM Transactions on Networking (TON)
IEEE/ACM Transactions on Networking (TON)
Efficient fair queueing using deficit round-robin
IEEE/ACM Transactions on Networking (TON)
Efficient support of delay and rate guarantees in an internet
Conference proceedings on Applications, technologies, architectures, and protocols for computer communications
Hierarchical packet fair queueing algorithms
IEEE/ACM Transactions on Networking (TON)
Division Algorithms and Implementations
IEEE Transactions on Computers
Tradeoffs between low complexity, low latency, and fairness with deficit round-robin schedulers
IEEE/ACM Transactions on Networking (TON)
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
LCN '05 Proceedings of the The IEEE Conference on Local Computer Networks 30th Anniversary
High Performance Switches and Routers
High Performance Switches and Routers
Cisco IOS Cookbook
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks
IEEE/ACM Transactions on Networking (TON)
Hybrid optimization for QoS control in IP Virtual Private Networks
Computer Networks: The International Journal of Computer and Telecommunications Networking
A scalable packet sorting circuit for high-speed WFQ packet scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Next Generation Networks: Perspectives and Potentials
Next Generation Networks: Perspectives and Potentials
WF2Q: worst-case fair weighted fair queueing
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
Fully hardware based WFQ architecture for high-speed QoS packet scheduling
Integration, the VLSI Journal
A calculus for network delay. I. Network elements in isolation
IEEE Transactions on Information Theory
NGN architecture: generic principles, functional architecture, and implementation
IEEE Communications Magazine
Design of packet-fair queuing schedulers using a RAM-based searching engine
IEEE Journal on Selected Areas in Communications
Computer Networks: The International Journal of Computer and Telecommunications Networking
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The increasing amount of real-time traffic carried over the Internet requires end-to-end quality of service (QoS) support. To this end, the QoS Schedulers, that are implemented in routers, assign the available bandwidth resources to packet flows according to their respective allocated rates. Packet Fair Queuing (PFQ) schedulers can provide fair service and low end-to-end delay bound to the traffic flows. However, they have higher implementation complexity compared to other algorithms, because of the requirements of tracking the system state, and searching for the packet to get service among all flows, that are queued at the outgoing interface. QoS scheduling is a data plane functionality, which requires hardware implementation for high speed router interfaces. The previous works on hardware implementation of PFQ schedulers are specific to certain algorithms, and they do not provide any results on real hardware platforms. In this paper, we present a general hardware design framework for PFQ schedulers, and apply this framework to the WF^2Q+ PFQ algorithm to demonstrate its properties. We carry out the entire implementation of the WF^2Q+ algorithm on an FPGA, and evaluate its performance with real traffic flows. In addition, we implement WFQ as a second PFQ algorithm to demonstrate the generality of the framework.