FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks

Authors:
Abdallah Merhebi;Otmane Ait Mohamed
Affiliations:
University of Concordia, Montréal, Québec, Canada;University of Concordia, Montréal, Québec, Canada
Venue:
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Year:
2005

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Hardware design and implementation of packet fair queuing algorithms for the quality of service support in the high-speed internet

Computer Networks: The International Journal of Computer and Telecommunications Networking

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Abstract

In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS) interfaces and ideal for the design of hybrid IP/ATM switches. Our contributions is an extension to an existing 4 channel scheduler architecture that combines the Highest Value First scheme and Round Robin scheme, to a modular multi channel scheduler design. The improvement we offer here compared to the previuous implementation is that we have used the existing 4 channel core module to build a higher order WF queuing system without decreasing its overall performance . As a result, our scheduler is general enough to accommodate ATM (UTOPIA Level3/4) , POS Phy Level3 (or PL3 for OC48) as well as POS Phy Level4 (or PL4 for OC192) interfaces.