High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Round-robin arbiter design and generation
Proceedings of the 15th international symposium on System Synthesis
Tiny Tera: A Packet Switch Core
IEEE Micro
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
An Efficient Client-to-Client Password-Authenticated Key Exchange Resilient to Server Compromise
PRDC '07 Proceedings of the 13th Pacific Rim International Symposium on Dependable Computing
Dynamic evolution of congestion trees: analysis and impact on switch architecture
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Queueing in high-performance packet switching
IEEE Journal on Selected Areas in Communications
High-radix crossbar switches enabled by proximity communication
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
The Journal of Supercomputing
VLSI micro-architectures for high-radix crossbar schedulers
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
The role of optics in future high radix switch design
Proceedings of the 38th annual international symposium on Computer architecture
Modeling Billion-Node Torus Networks Using Massively Parallel Discrete-Event Simulation
PADS '11 Proceedings of the 2011 IEEE Workshop on Principles of Advanced and Distributed Simulation
Co-design of channel buffers and crossbar organizations in NoCs architectures
Proceedings of the International Conference on Computer-Aided Design
Obtaining the optimal configuration of high-radix Combined switches
Journal of Parallel and Distributed Computing
Scalable high-radix router microarchitecture using a network switch organization
ACM Transactions on Architecture and Code Optimization (TACO)
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The interconnection network plays a key role in the overall performance achieved by high performance computing systems, also contributing an increasing fraction of its cost and power consumption. Current trends in interconnection network technology suggest that high-radix switches will be preferred as networks will become smaller (in terms of switch count) with the associated savings in packet latency, cost, and power consumption. Unfortunately, current switch architectures have scalability problems that prevent them from being effective when implemented with a high number of ports.In this paper, an efficient and cost-effective architecture for high-radix switches is proposed. The architecture, referred to as Partitioned Crossbar Input Queued (PCIQ), relies on three key components: a partitioned crossbar organization that allows the use of simple arbiters and crossbars, a packet based arbiter, and a mechanism to eliminate the switch-level HOL blocking.Under uniform traffic, maximum switch efficiency is achieved. Furthermore, switch-level HOL blocking is completely eliminated under hot-spot traffic, again delivering maximum throughput. Additionally, PCIQ inherently implements an efficient congestion management technique that eliminates all the network-wide HOL blocking. On the contrary, the previously proposed architectures either show poor performance or they require significantly higher costs than PCIQ (in both components and complexity).