The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
The Design of Innovation: Lessons from and for Competent Genetic Algorithms
The Design of Innovation: Lessons from and for Competent Genetic Algorithms
IEEE Transactions on Parallel and Distributed Systems
K-ary N-trees: High Performance Networks for Massively Parallel Architectures
K-ary N-trees: High Performance Networks for Massively Parallel Architectures
Stochastic Local Search: Foundations & Applications
Stochastic Local Search: Foundations & Applications
Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
Control Path Implementation for a Low-Latency Optical HPC Switch
HOTI '05 Proceedings of the 13th Symposium on High Performance Interconnects
The BlackWidow High-Radix Clos Network
Proceedings of the 33rd annual international symposium on Computer Architecture
Towards an efficient switch architecture for high-radix switches
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Metaheuristics: From Design to Implementation
Metaheuristics: From Design to Implementation
The role of optics in future high radix switch design
Proceedings of the 38th annual international symposium on Computer architecture
C-Switches: Increasing Switch Radix with Current Integration Scale
HPCC '11 Proceedings of the 2011 IEEE International Conference on High Performance Computing and Communications
Evaluation of an Alternative for Increasing Switch Radix
NCA '11 Proceedings of the 2011 IEEE 10th International Symposium on Network Computing and Applications
Optimal Configuration of High-Radix Combined Switches
PDP '12 Proceedings of the 2012 20th Euromicro International Conference on Parallel, Distributed and Network-based Processing
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High-radix switches reduce network cost and improve network performance, especially in large switch-based interconnection networks. However, there are some problems related to the integration scale to implement such switches in a single chip. An interesting alternative for building high-radix switches consists of combining several current smaller single-chip switches to obtain switches with a greater number of ports. A key design issue of this kind of high-radix switches is the internal switch configuration, specifically, the correspondence between the ports of these high-radix switches and the ports of their smaller internal single-chip switches. In this paper we use artificial intelligence and data mining techniques in order to obtain the optimal internal configuration of all the switches in the network of large supercomputers running parallel applications. Simulation results show that using the resultant switch configurations, it is possible to achieve similar performance as with single-chip switches with the same radix, which would be unfeasible with the current integration scale.