Obtaining the optimal configuration of high-radix Combined switches
Journal of Parallel and Distributed Computing
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In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency, since hop count is also reduced. However, there are some problems related to the integration scale to design such single-chip switches. In this paper we discuss key issues and evaluate an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller single-chip switches to obtain switches having greater number of ports. This approach is independent of the evolution of single-chip switches and remains valid as integration scale keeps evolving. Simulation results show that with a correct internal switch design, this alternative achieves almost the same performance as single-chip switches with the same number of ports, which would be unfeasible with the current integration scale.