Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The Asynchronous Transfer Mode: a tutorial
Computer Networks and ISDN Systems - Special issue on the ATM—asynchronous transfer mode
Computer organization & design: the hardware/software interface
Computer organization & design: the hardware/software interface
Pipelined memory shared buffer for VLSI switches
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
A flexible shared-buffer switch for ATM at Gb/s rates
Computer Networks and ISDN Systems
Supporting systolic and memory communication in iWarp
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Spider: A High-Speed Network Interconnect
IEEE Micro
A Parallel VLSI Video/Communication Controller
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Towards an efficient switch architecture for high-radix switches
Proceedings of the 2006 ACM/IEEE symposium on Architecture for networking and communications systems
Pipelined heap (priority queue) management for advanced scheduling in high-speed networks
IEEE/ACM Transactions on Networking (TON)
Microprocessors & Microsystems
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We describe the queue management block of ATLAS I, a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. All cells, in all queues, share one, common buffer space. These 3- and 4-stage pipelines handle events at the rate of one cell arrival or departure per clock cycle, and one credit arrival per clock cycle. The queue management block consists of two compiled SRAM's, pipeline bypass logic, and multi-port CAM and SRAM blocks that are laid out in full-custom and support special access operations. The full-custom part of queue management contains approximately 65 thousand transistors in logic and 14 Kbits in various special memories, it occupies 2.3 mm2, it consumes 270 mW (worst case), and it operates at 80 MHz (worst case) versus 50 MHz which is the required clock frequency to support the 622 Mb/s switch link rate.