Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
SIGCOMM '94 Proceedings of the conference on Communications architectures, protocols and applications
Pipelined memory shared buffer for VLSI switches
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Spider: A High-Speed Network Interconnect
IEEE Micro
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Reliable and efficient hop-by-hop flow control
IEEE Journal on Selected Areas in Communications
Memory optimization in single chip network switch fabrics
Proceedings of the 39th annual Design Automation Conference
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
IBM Journal of Research and Development
A trace-based framework for verifiable GALS composition of IPs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
ATLAS I is a single-chip ATM switch with 10 Gb/s throughput, a shared buffer, 3 priority levels, multicasting, load monitoring, and optional credit-based flow control. It is a 6-million-transistor chip in 0.35-micron CMOS technology. We present here its implementation; we report on the design complexity and silicon cost of the chip and of the individual functions that it supports. Based on these metrics, we evaluate the architecture of the switch. The evaluation points in the direction of increasing the cell buffer size and dropping VP/VC translation, while other possible modifications are also discussed. The cost of credit support (10% in chip area and 4% in chip power) is minuscule compared to its benefits, i.e. compared to what alternative architectures have to pay in order to achieve comparable performance levels.