An FPGA-based hardware accelerator for image processing
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Field programmable port extender (FPX) for distributed routing and queuing
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Reprogrammable network packet processing on the field programmable port extender (FPX)
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Proceedings of the 39th annual Design Automation Conference
Implementation Approaches for Reconfigurable Logic Applications
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Incremental reconfiguration for pipelined applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Control and Configuration Software for a Reconfigurable Networking Hardware Platform
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
TCP-Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware
HOTI '02 Proceedings of the 10th Symposium on High Performance Interconnects HOT Interconnects
Internet-based Tool for System-on-Chip Integration
MSE '03 Proceedings of the 2003 International Conference on Microelectronics Systems Education
Internet-based Tool for System-On-Chip Project Testing and Grading
MSE '03 Proceedings of the 2003 International Conference on Microelectronics Systems Education
Design of a Gigabit ATM Switch
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches
INFOCOM '97 Proceedings of the INFOCOM '97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution
Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Implementation of a Content-Scanning Module for an Internet Firewall
FCCM '03 Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Snort - Lightweight Intrusion Detection for Networks
LISA '99 Proceedings of the 13th USENIX conference on System administration
A survey of active network research
IEEE Communications Magazine
Design issues for high-performance active routers
IEEE Journal on Selected Areas in Communications
A scalable high-performance active network node
IEEE Network: The Magazine of Global Internetworking
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
| Hi-index | 0.00 |
Tools have been developed to automatically integrate and test networking systems in reconfigurable hardware. These tools dynamically generate circuits for Field Programmable Gate Arrays (FPGAs). A library of hardware-accelerated modules has been developed that processes Internet Protocol (IP) packets, performs header rule matching, scans pocket payloads, and implements per-flow queueing. Other functions can be added to the library as extensible modules.An integration tool was developed to enable a network administrator to specify how a customized system should examine, drop, buffer, and/or modify packets. This tool joins together modules from the library to create a composite circuit that performs multiple functions. The tool allows additional modules to be quickly added to the library and integrated into systems. The integration tool has been used to create circuits that perform Internet firewall, network intrusion detection, network intrusion prevention, and Denial of Service (DoS) attack protection functions.A test tool was developed to automatically verify that circuits created by the integration tool run properly in reconfigurable hardware. Circuits created by the integration tool are deployed into a Field-programmable Port Extender (FPX) platform. As new modules were added to the library, the test tool reconfigured the logic on the FPX, injected traffic, and monitored the resulting packets.By using hardware, not software, networking system can process millions of packets per second. Together, the integration and test tools simplify the otherwise difficult task of developing reconfigurable hardware for networking systems and testing them at Gigabit per second rates.