Building a robust software-based router using network processors
SOSP '01 Proceedings of the eighteenth ACM symposium on Operating systems principles
Memory optimization in single chip network switch fabrics
Proceedings of the 39th annual Design Automation Conference
A fully-programmable memory management system optimizing queue handling at multi gigabit rates
Proceedings of the 40th annual Design Automation Conference
Queue Management for QoS Provision Build on Network Processor
FTDCS '03 Proceedings of the The Ninth IEEE Workshop on Future Trends of Distributed Computing Systems
IBM PowerNP network processor: Hardware, software, and applications
IBM Journal of Research and Development
Beyond best effort: router architectures for the differentiated services of tomorrow's Internet
IEEE Communications Magazine
Scalable architectures for integrated traffic shaping and link scheduling in high-speed ATM switches
IEEE Journal on Selected Areas in Communications
Designing communication subsystems for high-speed networks
IEEE Network: The Magazine of Global Internetworking
Advanced packet segmentation and buffering algorithms in network processors
Transactions on High-Performance Embedded Architectures and Compilers IV
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One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we analyze the performance bottlenecks of various data memory managers integrated in typical Network Processing Units (NPUs). We expose the performance limitations of software implementations utilizing the RISC processing cores typically found in most NPU architectures and we identify the requirements for hardware assisted memory management in order to achieve wire-speed operation at gigabit per second rates. Furthermore, we describe the architecture and performance of a hardware memory manager that fulfills those requirements. This memory manager, although it is implemented in a reconfigurable technology, it can provide up to 6.2Gbps of aggregate throughput, while handling 32K independent queues.