Design of an efficient memory subsystem for network processor

Authors:
Shuguang Gong;Huawei Li;Yufeng Xu;Tong Liu;Xiaowei Li
Affiliations:
Graduate School of the Chinese Academy of Sciences, Beijing, China;Graduate School of the Chinese Academy of Sciences, Beijing, China;Graduate School of the Chinese Academy of Sciences, Beijing, China;Graduate School of the Chinese Academy of Sciences, Beijing, China;Graduate School of the Chinese Academy of Sciences, Beijing, China
Venue:
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Year:
2005

Citing 8
Cited 0

A Fixed Optimum Cell-Size for Records of Various Lengths

Journal of the ACM (JACM)
On-chip communication architecture for OC-768 network processors

Proceedings of the 38th annual Design Automation Conference
System-level performance optimization of the data queueing memory management in high-speed network processors

Proceedings of the 39th annual Design Automation Conference
Programmable Networks: Selected Challenges in Computer Networking

Computer
A fully-programmable memory management system optimizing queue handling at multi gigabit rates

Proceedings of the 40th annual Design Automation Conference
Efficient use of memory bandwidth to improve network processor throughput

Proceedings of the 30th annual international symposium on Computer architecture
Predictions for the core of the network

IEEE Internet Computing
Wide-area Internet traffic patterns and characteristics

IEEE Network: The Magazine of Global Internetworking

Quantified Score

Hi-index	0.00

Visualization

Abstract

The rapid growth of backbone network traffic increases the gaps among the available network bandwidth, the CPU computation power and the memory bandwidth. The memory bandwidth has become the main performance bottleneck of network processor. In this paper, an efficient memory subsystem design is proposed which combines dynamic memory allocation and a novel page-based memory access algorithm. The dynamic memory allocation achieves fast random packet access and flexible queue management. Utilizing the paged-based memory access algorithm, an efficient design of memory controller is proposed and high throughput can be implemented in the network processor.