Task partitioning for multi-core network processors

  • Authors:

  • Robert Ennals;Richard Sharp;Alan Mycroft

  • Affiliations:

  • Intel Research Cambridge, Cambridge, UK;Intel Research Cambridge, Cambridge, UK;Computer Laboratory, Cambridge University, Cambridge, UK

  • Venue:
  • CC'05 Proceedings of the 14th international conference on Compiler Construction
  • Year:
  • 2005

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Abstract

Network processors (NPs) typically contain multiple concurrent processing cores. State-of-the-art programming techniques for NPs are invariably low-level, requiring programmers to partition code into concurrent tasks early in the design process. This results in programs that are hard to maintain and hard to port to alternative architectures. This paper presents a new approach in which a high-level program is separated from its partitioning into concurrent tasks. Designers write their programs in a high-level, domain-specific, architecturally-neutral language, but also provide a separate Architecture Mapping Script (AMS). An AMS specifies semantics-preserving transformations that are applied to the program to re-arrange it into a set of tasks appropriate for execution on a particular target architecture. We (i) describe three such transformations: pipeline introduction, pipeline elimination and queue multiplexing; and (ii) specify when each can be safely applied. As a case study we describe an IP packet-forwarder and present an AMS script that partitions it into a form capable of running at 3Gb/s on an Intel IXP2400 Network Processor.