A high level development, modeling and simulation methodology for complex multicore network processors

Authors:
Gianni Antichi;Christian Callegari;Andrea Di Pietro;Domenico Ficara;Stefano Giordano;Fabio Vitucci;Massimiliano Meneghin;Massimo Torquati;Marco Vanneschi;Massimo Coppola
Affiliations:
Dept. of Information Engineering, University of Pisa, Italy;Dept. of Information Engineering, University of Pisa, Italy;Dept. of Information Engineering, University of Pisa, Italy;Dept. of Information Engineering, University of Pisa, Italy;Dept. of Information Engineering, University of Pisa, Italy;Dept. of Information Engineering, University of Pisa, Italy;Computer Science Dept., University of Pisa, Italy;Computer Science Dept., University of Pisa, Italy;Computer Science Dept., University of Pisa, Italy;ISTI-CNR, Pisa, Italy
Venue:
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
Year:
2009

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Abstract

Network Processors (NPs) are attracting and powerful platforms for the fast development of high performance network applications. However, despite their greater flexibility and limited cost with respect to specialized hardware design, NP still face developers with significant difficulties. As they target complex and high-performance applications, programmers are often forced to write assembly code in order to better exploit the hardware. In this paper we propose an approach to NP programming which is based on a three-phase development methodology, and we apply it to Intel NPs of the IXP2XXX family. By exploiting a composition of software tools, a high-level definition of the application is turned first into a distributed program, then into an NP prototype, and finally into an efficient NP executable. The methodology we describe takes advantage of the ASSIST technology, which allows for the porting, testing, modeling and profiling of parallel applications on a cluster of standard PCs. We developed a C library that acts as a communication layer, hiding the hardware details of NP programming and allowing for high performance code development. The ultimate goal of this approach is to let programmers write C code, exploiting ASSIST-provided hints to (1) perform functional debugging and performance analysis and (2) to experiment with different parallel structures. The resulting code can be then directly compiled for the NP without modifications, largely reducing the overall coding effort.